The present invention relates generally to semiconductor fabrication, and more particularly to methods for fabricating improved ultra-large scale integration (ULSI) semiconductor devices such as ULSI metal oxide silicon field effect transistors (MOSFETs).
Semiconductor chips or wafers are used in many applications, including as processor chips for computers, and as integrated circuits and as flash memory for hand held computing devices, wireless telephones, and digital cameras. Regardless of the application, it is desirable that a semiconductor chip hold as many circuits or memory cells as possible per unit area. In this way, the size, weight, and energy consumption of devices that use semiconductor chips advantageously is minimized, while nevertheless improving the memory capacity and computing power of the devices.
A common circuit component of semiconductor chips is the transistor. In ULSI semiconductor chips, a transistor is established by forming a polysilicon gate on a silicon substrate, and then forming a source region and a drain region side by side in the substrate beneath the gate by implanting appropriate dopant materials into the areas of the substrate that are to become the source and drain regions. The gate is insulated from the source and drain regions by a thin gate oxide layer, with small portions of the source and drain regions, referred to as xe2x80x9cextensionsxe2x80x9d, extending toward and virtually under the gate. This generally-described structure cooperates to function as a transistor.
As the dimensions of MOSFETs desirably are reduced as discussed above, it will be readily appreciated that the depth to which the source and drain extensions of a transistor penetrates the silicon substrate decreases. While shallow source/drain extensions promote immunity from the deleterious ramifications of so-called short-channel effect and facilitate ever-smaller integrated circuits, unfortunately the limits of current ion implantation technology render it difficult at best to form ultra-shallow source/drain regions, i.e., regions having depths of 30 nanometers or less.
The present invention recognizes that laser annealing might instead be used to form ultra-shallow source/drain regions. However, the present invention understands that the use of a metal film to absorb the laser energy as has been proposed in other applications is undesirable. This is because the film must be stripped after use by a wet chemical etch, which adds cost and complexity, and the film and chemical process furthermore might possibly contaminate the silicon chip and render it less suitable for its intended purpose than might otherwise be hoped. Fortunately, the present invention recognizes that laser annealing can be used to precisely form ultra-shallow source/drain extensions without using a metal film.
A method is disclosed for establishing at least one transistor on a semiconductor device. The method includes forming one or more MOS gates on a semiconductor substrate, and depositing dopant on first regions of the substrate. Then, a silicidizing substance is implanted in the first regions to silicidize the first regions. The method then envisions directing a laser beam against the first regions to move the dopant into the substrate for establishing source and drain regions.
In a preferred embodiment, a protective layer is deposited on the gate, and a first pre-amorphization (PAI) substance is implanted into the substrate prior to the step of depositing dopant. The protective layer substantially prevents implanting the first PAI substance through the layer into the gate. Also, a sidewall spacer is established on the gate after the step of implanting the first PAI substance, and then a second PAI substance is implanted into the substrate, with the protective layer and sidewall spacer substantially preventing implanting the second PAI substance through the layer and spacer. As described in greater detail below, the first PAI substance defines the contours of source and drain extensions, and the second PAI substance defines the contours of deep source/drain junctions.
In accordance with the present invention, the laser beam preferably is established such that regions with PAI substances (i.e., pre-amorphized regions) are at least partially melted thanks to the selective absorption of laser light induced by the silicidizing of these regions. The melting of the pre-amorphized regions causes the dopant to move into the pre-amorphized regions, and single crystal silicon regions are not melted, thereby substantially preventing the dopant from moving into the single crystal regions. If desired, the protective layer can be removed from the gate prior to implanting the dopant such that at least one dopant substance is implanted into the gate. A semiconductor device made according to the method, and a digital processing apparatus incorporating the semiconductor device, are also disclosed.
In another aspect, a method for making an ultra-large scale integration (ULSI) semiconductor device includes forming at least one gate on at least one semiconductor substrate, and pre-amorphizing first regions of the substrate while not pre-amorphizing second regions of the substrate. Dopant is provided on the substrate next to the gate. Then, the first regions are caused to at least partially melt, in contrast to the second regions, which do not melt, thereby causing the dopant to enter only the first regions.
In yet another aspect, a semiconductor device includes at least one transistor that in turn includes a gate disposed on a silicidized silicon substrate. The transistor further includes first regions that have dopant driven into them by virtue of the first regions having been melted by a laser. These first regions define source and drain regions for ULSI MOSFETs. Preferably, the first regions are pre-amorphized prior to laser annealing.
Other features of the present invention are disclosed or apparent in the section entitled xe2x80x9cDETAILED DESCRIPTION OF THE INVENTIONxe2x80x9d.